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? freescale semiconductor, inc., 2009. all rights reserved. freescale semiconductor technical data the mpc8241 combines a powerpc? mpc603e core with a pci bridge so that system designers can rapidly design systems using peripherals designed for pci and other standard interfaces. also, a high-performance memory controller supports various types of rom and sdram. the mpc8241 is the second of a family of products that provide system-level support for industry-standard interfaces with an mpc603e processor core. this hardware specification describes pertinent electrical and physical characteristics of the mpc8241, which is based on the mpc8245 design. for functional characteristics of the processor, refer to the mpc8245 integrated processor reference manual (mpc8245um). for published errata or updates to this document, visit the web site listed on the back cover of the document. 1overview the mpc8241 integrated processor is composed of a peripheral logic block and a 32-bit superscalar mpc603e core, as shown in figure 1 . document number: MPC8241EC rev. 10, 02/2009 contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4. electrical and thermal characteristics . . . . . . . . . . . . 6 5. package description . . . . . . . . . . . . . . . . . . . . . . . . . 31 6. pll configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7. system design information . . . . . . . . . . . . . . . . . . . 42 8. ordering information . . . . . . . . . . . . . . . . . . . . . . . . 52 9. document revision history . . . . . . . . . . . . . . . . . . . 54 mpc8241 integrated processor hardware specifications
mpc8241 integrated processor hardware specifications, rev. 10 2 freescale semiconductor overview figure 1. mpc8241 block diagram peripheral logic bus instruction system integer load/store floating- data instruction 16-kbyte processor core block processor pll (64-bit) two-instruction fetch (64-bit) two-instruction dispatch 64-bit branch processing unit (bpu) mpc8241 register unit (sru) unit (iu) unit (lsu) point unit (fpu) instruction cache mmu mmu additional features: ? prog i/o with watchpoint ? jtag/cop interface ? power management address translator dll fanout buffers pci arbiter message unit (with i 2 o) i 2 c controller dma controller interrupt controller/ pic timers pci bus interface unit memory controller data path ecc controller central control unit 32-bit osc_in five request/grant pairs i 2 c 5 irqs/ peripheral logic block peripheral logic pll pci bus data (64-bit) address data bus (32- or 64-bit) memory/rom/ port x control/address pci interface clocks 16 serial interrupts configuration registers (32-bit) with 8-bit parity or ecc pci_sync_in sdram_sync_in watchpoint facility duart performance monitor sdram clocks 16-kbyte data cache 16-kbyte instruction cache unit
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 3 features the peripheral logic integrates a pci bridge, dual universal asynchronous receiver/transmitter (duart), memory controller, dma controller, pic interrupt controller, a message unit (and i 2 o interface), and an i 2 c controller. the processor core is a full-featured, high-performance processor with floating-point support, memory management, 16-kbyte instruction cache, 16-kbyte data cache, and power management features. the integration reduces the overall packagi ng requirements and the number of discrete devices required for an embedded system. an internal peripheral logic bus interfaces the processo r core to the peripheral logic. the core can operate at a variety of frequencies, allo wing the designer to trade performance for power consumption. the processor core is clocked from a separate pll that is referenced to the peripheral logic pll, allowing the microprocessor and the peripheral logic block to opera te at different frequencies while maintaining a synchronous bus interface. the interface uses a 64- or 32-bit data bus (depending on memory data bus width) and a 32-bit address bus along with control signa ls that enable the interface between the processor and peripheral logic to be optimized for performance. pci accesses to the mpc8241 memory space are passed to the processor bus for snooping when snoop mode is enabled. the general-purpose processor core and peripheral l ogic serve a variety of embedded applications. the mpc8241 can be used as either a pci host or pci agent controller. 2features major features of the mpc8241 are as follows: ? processor core ? high-performance, superscalar processor core ? integer unit (iu), floating-point unit (fpu) (software enabled or disabled), load/store unit (lsu), system register unit (sru), and a branch processing unit (bpu) ? 16-kbyte instruction cache ? 16-kbyte data cache ? lockable l1 caches?entire cache or on a per-way basis up to three of four ways ? dynamic power manageme nt?supports 60x nap, doze, and sleep modes ? peripheral logic ? peripheral logic bus ? various operating frequencies and bus divider ratios ? 32-bit address bus, 64-bit data bus ? full memory coherency ? decoupled address and data buses for pi pelining of peripheral logic bus accesses ? store gathering on peripheral logic bus-to-pci writes ? memory interface ? up to 2 gbytes of sdram memory ? high-bandwidth data bus (32- or 64-bit) to sdram ? programmable timing for sdram ? one to 8 banks of 16-, 64-, 128-, 256-, or 512-mbit memory devices
mpc8241 integrated processor hardware specifications, rev. 10 4 freescale semiconductor features ? write buffering for pci and processor accesses ? normal parity, read-modify-write (rmw), or ecc ? data-path buffering between memory interface and processor ? low-voltage ttl logic (lvttl) interfaces ? 272 mbytes of base and extended rom/flash/portx space ? base rom space for 8-bit data path or same size as the sdram data path (32- or 64-bit) ? extended rom space for 8-, 16-, 32-bit gathering data path, 32- or 64-bit (wide) data path ? portx: 8-, 16-, 32-, or 64-bit general-purpose i/o port using rom controller interface with programmable address strobe timing, data ready input signal (drdy ), and 4 chip selects ? 32-bit pci interface ? operates up to 66 mhz ? pci 2.2-compatible ? pci 5.0-v tolerance ? dual address cycle (dac) for 64-bit pci addressing (master only) ? pci locked accesses to memory ? accesses to pci memory, i/o, and configuration spaces ? selectable big- or little endian operation ? store gathering of processor-to-pci write and pci-to-memory write accesses ? memory prefetching of pci read accesses ? selectable hardware-enforced coherency ? pci bus arbitration unit (five request/grant pairs) ? pci agent mode capability ? address translation with two inbound and outbound units (atu) ? internal configuration registers accessible from pci ? two-channel integrated dma controller (writes to rom/portx not supported) ? direct mode or chaining mode (automatic linking of dma transfers) ? scatter gathering?read or write discontinuous memory ? 64-byte transfer queue per channel ? interrupt on completed segment, chain, and error ? local-to-local memory ? pci-to-pci memory ? local-to-pci memory ? pci memory-to-local memory ? message unit ? two doorbell registers ? two inbound and two outbound messaging registers ?i 2 o message interface
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 5 general parameters ?i 2 c controller with full master/slave s upport that accepts broadcast messages ? programmable interrupt controller (pic) ? five hardware interrupts (irqs) or 16 serial interrupts ? four programmable timers with cascade ? two (dual) universal asynchronous receiver/transmitters (uarts) ? integrated pci bus and sdram clock generation ? programmable pci bus and memory interface output drivers ? system level performance monitor facility ? debug features ? memory attribute and pci attribute signals ? debug address signals ?miv signal?marks valid address and da ta bus cycles on the memory bus ? programmable input and output signals with watchpoint capability ? error injection/capture on data path ? ieee std. 1149.1 (jtag)/test interface 3 general parameters the following list summarizes the general parameters of the mpc8241: technology 0.25 m cmos, five-layer metal die size 49.2 mm 2 transistor count 4.5 million logic design fully static packages surface-mount 357 (thick substrate and thick mold cap) plastic ball grid array (pbga) core power supply 1.8 v 100 mv dc (nominal; see table 2 for details and recommended operating conditions) i/o power supply 3.0 to 3.6 v dc
mpc8241 integrated processor hardware specifications, rev. 10 6 freescale semiconductor electrical and thermal characteristics 4 electrical and thermal characteristics this section provides the ac and dc electrical specifications and thermal characteristics for the mpc8241. 4.1 dc electrical characteristics this section covers ratings, conditions, and other characteristics. 4.1.1 absolute maximum ratings this section describes the mpc8241 dc electrical characteristics. table 1 provides the absolute maximum ratings. table 1. absolute maximum ratings characteristic 1 symbol range unit supply voltage?cpu core and peripheral logic v dd ?0.3 to 2.1 v supply voltage?memory bus drivers, pci and standard i/o buffers gv dd _ov dd ?0.3 to 3.6 v supply voltage?plls av dd /av dd 2 ?0.3 to 2.1 v supply voltage?pci reference lv dd ?0.3 to 5.4 v input voltage 2 v in ?0.3 to 3.6 v operational die-junction temperature range t j 0 to 105 ?c c storage temperature range t stg ?55 to 150 ?c c notes: 1. ta b l e 2 provides functional and tested operating conditions. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. pci inputs with lv dd = 5 v 5% v dc may be correspondingly stressed at voltages exceeding lv dd + 0.5 v dc.
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 7 electrical and thermal characteristics 4.1.2 recommended operating conditions table 2 provides the recommended operating conditions for the mpc8241. table 2. recommended operating conditions 1 characteristic symbol recommended value unit notes supply voltage v dd 1.8 100 mv v 2 i/o buffer supply for pci and standard; supply voltages for memory bus drivers gv dd _ov dd 3.3 0.3 v 2 cpu pll supply voltage av dd 1.8 100 mv 2 pll supply voltage?peripheral logic av dd 21.8 100 mv v 2 pci reference lv dd 5.0 5% v 4, 5, 6 3.3 0.3 v 5, 6, 7 input voltage pci inputs v in 0 to 3.6 or 5.75 v 4, 7 all other inputs 0 to 3.6 v 8 die-junction temperature t j 0 to 105 ?c c notes: 1. freescale has tested these operating conditions and recommends them. proper device operation outside of these conditions is not guaranteed. 2. caution: gv dd _ov dd must not exceed v dd /av dd /av dd 2 by more than 1.8 v at any time including during power-on reset. note that gv dd _ov dd pins are all shorted together: this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. connections should not be made to individual pwrring pins. 3. caution: v dd /av dd /av dd 2 must not exceed gv dd _ov dd by more than 0.6 v at any time, including during power-on reset. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. pci pins are designed to withstand lv dd + 0.5 v dc when lv dd is connected to a 5.0 v dc power supply. 5. caution: lv dd must not exceed v dd /av dd /av dd 2 by more than 5.4 v at any time, including during power-on reset. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 6. caution: lv dd must not exceed gv dd _ov dd by more than 3.0 v at any time, including during power-on reset. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 7. pci pins are designed to withstand lv dd + 0.5 v dc when lv dd is connected to a 3.3 v dc power supply. 8. caution: input voltage (v in ) must not be greater than the supply voltage (v dd /av dd /av dd 2) by more than 2.5 v at all times including during power-on reset. input voltage (v in ) must not be greater than gv dd _ov dd by more than 0.6 v at all times including during power-on reset.
mpc8241 integrated processor hardware specifications, rev. 10 8 freescale semiconductor electrical and thermal characteristics figure 2 shows supply voltage sequencing and separation cautions. figure 2. supply voltage sequencing and separation cautions gv dd _ov dd /(lv dd @ 3.3 v - - - -) v dd /av dd /av dd 2 lv dd @ 5 v time 3.3 v 5 v 2 v 0 3 6 5 5 6 2 dc power supply voltage reset configuration pins hrst_cpu and hrst_ctrl pll relock time 3 100 s nine external memory asserted 255 external memory hrst_cpu and hrst_ctrl v dd stable power supply ramp up 2 see note 1 clock cycles 3 clock cycles setup time 4 vm = 1.4 v one external memory clock cycle 5 maximum rise time must be less than notes: 1. numbers associated with waveform separations correspond to caution numbers listed in ta ble 2 . 2. see the cautions section of ta b l e 2 for details on this topic. 3. refer to ta b l e 8 for details on pll relock and reset signal assertion timing requirements. 4. refer to ta b l e 1 0 for details on reset configuration pin setup timing requirements. 5. hrst_cpu /hrst_ctrl must transition from a logic 0 to a logic 1 in less than one sdram_sync_in clock cycle for the device to be in the nonreset state. 6. pll_cfg signals must be driven on reset and must be held for at least 25 clock cycles after the negation of hrst_ctrl and hrst_cpu negate in order to be latched. pll 6
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 9 electrical and thermal characteristics figure 3 shows the undershoot and overshoot voltage of the memory interface. figure 3. overshoot/undershoot voltage figure 4 and figure 5 show the undershoot and overshoot voltage of the pci interface for the 3.3- and 5-v signals, respectively. figure 4. maximum ac waveforms for 3.3-v signaling gnd/gndring gnd/gndring ? 0.3 v gnd/gndring ? 1.0 v not to exceed 10% gv dd _ov dd of t sdram_clk gv dd _ov dd + 5% 4 v v ih v il undervoltage waveform overvoltage waveform 11 ns (min) +7.1 v 7.1 vp-to-p (min) 4 ns (max) ?3.5 v 7.1 vp-to-p (min) 62.5 ns +3.6 v 0 v 4 ns (max)
mpc8241 integrated processor hardware specifications, rev. 10 10 freescale semiconductor electrical and thermal characteristics figure 5. maximum ac waveforms for 5-v signaling 4.2 dc electrical characteristics table 3 provides the dc electrical characteristics fo r the mpc8241 at recommended operating conditions. table 3. dc electrical specifications characteristics conditions symbol min max unit notes input high voltage pci only, except pci_sync_in v ih 0.65 gv dd _ov dd lv dd v1 input low voltage pci only, except pci_sync_in v il ?0.3 gv dd _ov dd v input high voltage all other pins, including pci_sync_in (gv dd _ov dd = 3.3 v) v ih 2.0 3.3 v input low voltage all inputs, including pci_sync_in v il gnd/gndring 0.8 v 2 input leakage current for pins using drv_pci driver 0.5 v v in 2.7 v @ lv dd = 4.75 v i l ? 70 a 3 input leakage current all others lv dd = 3.6 v gv dd _ov dd 3.465 v i l ? 10 a 3 output high voltage i oh = driver dependent (gv dd _ov dd = 3.3 v) v oh 2.4 ? v 4 output low voltage i ol = driver dependent (gv dd _ov dd = 3.3 v) v ol ?0.4v4 undervoltage waveform overvoltage waveform 11 ns (min) +11 v 11 v p-to-p (min) 4 ns (max) ?5.5 v 10.75 v p-to-p (min) 62.5 ns +5.25 v 0 v 4 ns (max)
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 11 electrical and thermal characteristics 4.2.1 output driver characteristics table 4 provides information on the characteristics of the output drivers referenced in table 16 . the values are preliminary estimates from an ibis model and are not tested. capacitance v in = 0 v, f = 1 mhz c in ? 16.0 pf notes: 1. see ta ble 1 6 for pins with internal pull-up resistors. 2. all grounded pins are connected together. 3. leakage current is measured on input and output pins in the high-impedance state. the leakage current is measured for nominal gv dd _ov dd /lv dd and v dd or both gv dd _ov dd /lv dd and v dd must vary in the same direction. 4. see ta b l e 4 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin as listed in ta b l e 1 6 . table 4. drive capability of mpc8241 output pins 5, 6 driver type programmable output impedance ( ) supply voltage i oh i ol unit notes drv_std_mem 20 (default) gv dd _ov dd = 3.3 v 36.6 18.0 ma 2, 4 40 18.6 9.2 ma 2, 4 drv_pci 20 12.0 12.4 ma 1, 3 40 (default) 6.1 6.3 ma 1, 3 drv_mem_ctrl drv_pci_clk drv_mem_clk 6 (default) 89.0 42.3 ma 2, 4 20 36.6 18.0 ma 2, 4 40 18.6 9.2 ma 2, 4 notes: 1. for drv_pci, i oh read from the ibis listing in the pull-up mode, i(min) column, at the 0.33-v label by interpolating between the 0.3- and 0.4-v table entries current values which corresponds to the pci v oh = 2.97 = 0.9 gv dd _ov dd (gv dd _ov dd = 3.3 v) where table entry voltage = gv dd _ov dd ? pci v oh . 2. for all others with gv dd _ ov dd = 3.3 v, i oh read from the ibis listing in the pull-up mode, i(min) column, at the 0.9-v table entry which corresponds to the v oh = 2.4 v where table entry voltage = gv dd _ov dd ? v oh . 3. for drv_pci, i ol read from the ibis listing in the pull-down mode, i(min) column, at 0.33 v = pci v ol = 0.1 gv dd _ov dd (gv dd _ov dd = 3.3 v) by interpolating between the 0.3- and 0.4-v table entries. 4. for all others with gv dd _ov dd = 3.3 v, i ol read from the ibis listing in the pull-down mode, i(min) column, at the 0.4-v table entry. 5. see driver bit details for output driver control register (0x73) in the mpc8245 integrated processor reference manual . 6. see chip errata no. 19 in the mpc8245/mpc8241 integrated processor chip errata . table 3. dc electrical specifications (continued) characteristics conditions symbol min max unit notes
mpc8241 integrated processor hardware specifications, rev. 10 12 freescale semiconductor electrical and thermal characteristics 4.3 power characteristics table 5 provides preliminary estimated power consumption data for the mpc8241. table 5. preliminary power consumption mode pci bus clock/memory bus clock cpu clock frequency (mhz) unit notes 33/66/133 33/66/166 33/66/200 33/100/200 66/100/200 66/66/ 266 66/133/ 266 typical 0.7 0.8 1.0 1.0 1.0 1.5 1.8 w 1, 5 max?cfp0.81.01.21.31.31.92.1w1, 2 max?int 0.8 0.9 1.0 1.2 1.2 1.6 1.8 w 1, 3 doze 0.5 0.6 0.7 0.8 0.8 1.0 1.3 w 1, 4, 6 nap 0.2 0.2 0.3 0.4 0.4 0.4 0.7 w 1, 4, 6 sleep 0.2 0.2 0.2 0.2 0.3 0.2 0.4 w 1, 4, 6 i/o power supplies 7 mode minimum maximum unit notes gv dd _ov dd 500 1130 mw 8 notes: 1. the values include v dd , av dd , and av dd 2 but do not include i/o supply power. 2. maximum?fp power is measured at v dd = 1.9 v with dynamic power management enabled while running an entirely cache-resident, looping, floating-point multiplication instruction. 3. maximum?int power is measured at v dd = 1.9 v with dynamic power management enabled while running entirely cache-resident, looping, integer instructions. 4. power saving mode maximums are measured at v dd = 1.9 v while the device is in doze, nap, or sleep mode. 5. typical power is measured at v dd = av dd = 1.8 v, gv dd _ov dd = 3.3 v where a nominal fp value, a nominal int value, and a value where there is a continuous flush of cache lines with alternating ones and zeros on 64-bit boundaries to local memory are averaged. 6. power saving mode data measured with only two pci_clks and two sdram_clks enabled. 7. power consumption of pll supply pins (av dd and av dd 2) < 15 mw, guaranteed by design, but not tested. 8. the typical maximum gv dd _ov dd value resulted from the mpc8241 operating at the fastest frequency combination of 66:133:266 (pci:mem:cpu) mhz and performing continuous flushes of cache lines with alternating ones and zeros to pci memory and on 64-bit boundaries to local memory.
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 13 electrical and thermal characteristics 4.4 thermal characteristics table 6 provides the package thermal characteristics for the mpc8241. for details, see section 7.7, ?thermal management.? 4.5 ac electrical characteristics after fabrication, functional parts are sorted by maximum processor core frequency as shown in table 7 and tested for conformance to the ac specifications for that frequency. the processor core frequency is determined by the bus (pci_sync_in) clock frequenc y and the settings of the pll_cfg[0:4] signals. parts are sold by maximum processor core frequency. see section 8, ?ordering information.? table 6. thermal characterization data rating thermal test board description symbol value 7 (166- and 200-mhz parts) value 7 (266-mhz part) unit notes junction-to-ambient natural convection single-layer board (1s) r ja 38 28 c/w 1, 2 junction-to-ambient natural convection four-layer board (2s2p) r jma 25 20 c/w 1, 3 junction-to-ambient (@200 ft/min) single-layer board (1s) r jma 31 22 c/w 1, 3 junction-to-ambient (@200 ft/min) four-layer board (2s2p) r jma 22 17 c/w 1, 3 junction-to-board (bottom) four-layer board (2s2p) r jb 17 11 c/w 4 junction-to-case (top) single-layer board (1s) r jc 87c/w5 junction-to-package top natural convection jt 22c/w6 notes: 1. junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 2. per semi g38-87 and eia/jesd51-2 with the board horizontal. 3. per eia/jesd51-6 with the board horizontal. 4. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperature used for the case temperature. 6. thermal characterization parameter indicating the temperature difference between package top and the junction temperature per eia/jesd51-2. 7. note that the 166- and 200-mhz parts are in a two-layer package and the 266-mhz part is in a four-layer package, which causes the two package types to have different thermal characterization data.
mpc8241 integrated processor hardware specifications, rev. 10 14 freescale semiconductor electrical and thermal characteristics table 7 provides the operating frequency informati on for the mpc8241 at recommended operating conditions (see table 2 ) with lv dd = 3.3 v 0.3 v. 4.5.1 clock ac specifications table 8 provides the clock ac timing specifications at recommended operating conditions, as defined in section 4.5.2, ?input ac timing specifications.? these specifications are for the default driver strengths indicated in table 4 . figure 6 shows the pci_sync_in input clock timing diagram with the labeled number items listed in table 8 . table 7. operating frequency characteristic 166 mhz 200 mhz 266 mhz unit v dd /av dd /av dd 2 = 1.8 100 mv min max min max min max processor frequency (cpu) 100 166 100 200 100 266 mhz memory bus frequency 33 83 33 100 33 133 mhz pci input frequency 25?66 mhz caution: the pci_sync_in frequency and pll_cfg[0:4] settings must be chosen such that the resulting peripheral logic/memory bus frequency and cpu (core) frequencies do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0:4] signal description in section 6, ?pll configuration,? for valid pll_cfg[0:4] settings and pci_sync_in frequencies. table 8. clock ac timing specifications at recommended operating conditions (see ta b l e 2 ) with lv dd = 3.3 v 0.3 v num characteristics and conditions min max unit notes 1 frequency of operation (pci_sync_in) 25 66 mhz 2, 3 pci_sync_in rise and fall times ? 2.0 ns 1 4 pci_sync_in duty cycle measured at 1.4 v 40 60 % 5a pci_sync_in pulse width high measured at 1.4 v 6 9 ns 2 5b pci_sync_in pulse width low measured at 1.4 v 6 9 ns 2 7 pci_sync_in jitter ? 200 ps 8a pci_clk[0:4] skew (pin-to-pin) ? 250 ps 8b sdram_clk[0:3] skew (pin-to-pin) ? 190 ps 3 10 internal pll relock time ? 100 s 2, 4, 5 15 dll lock range with dll_extend = 0 (disabled) and normal tap delay; (default dll mode) see figure 7 ns 6 16 dll lock range for other modes see figure 8 through figure 10 ns 6 17 frequency of operation (osc_in) 25 66 mhz 19 osc_in rise and fall times ? 5 ns 7 20 osc_in duty cycle measured at 1.4 v 40 60 %
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 15 electrical and thermal characteristics figure 6 shows the pci_sync_in input clock timing diagram, and figure 7 through figure 10 show the dll locking range loop delay ve rsus frequency of operation. figure 6. pci_sync_in input clock timing diagram 21 osc_in frequency stability ? 100 ppm notes : 1. rise and fall times for the pci_sync_in input are measured from 0.4 through 2.4 v. 2. specification value at maximum frequency of operation. 3. pin-to-pin skew includes quantifying the additional amount of clock skew (or jitter) from the dll besides any intentional ske w added to the clocking signals from the variable length dll synchronization feedback loop, that is, the amount of variance between the internal sys_logic_clk and the sdram_sync_in signal after the dll is locked. while pin-to-pin skew between sdram_clks can be measured, the relationship between the internal sys_logic_clk and the external sdram_sync_in cannot be measured and is guaranteed by design. 4. relock time is guaranteed by design and characterization. relock time is not tested. 5. relock timing is guaranteed by design. pll-relock time is the maximum amount of time required for pll lock after a stable v dd and pci_sync_in are reached during the reset sequence. this specification also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hrst_cpu /hrst_ctrl must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the reset sequence. 6. dll_extend is bit 7 of the pmc2 register <72>. n is a non-zero integer (see figure 7 through figure 10 ). t clk is the period of one sdram_sync_out clock cycle in ns. t loop is the propagation delay of the dll synchronization feedback loop (pc board runner) from sdram_sync_out to sdram_sync_in in ns; 6.25 inches of loop length (unloaded pc board runner) corresponds to approximately 1 ns of delay. for details about how figure 7 through figure 10 may be used, refer to the freescale application note an2164, mpc8245/mpc8241 memory clock design guidelines, for details on mpc8241 memory clock design. 7. rise and fall times for the osc_in input are guaranteed by design and characterization. osc_in input rise and fall times are not tested. table 8. clock ac timing specifications (continued) at recommended operating conditions (see ta b l e 2 ) with lv dd = 3.3 v 0.3 v num characteristics and conditions min max unit notes 5a 5b vm vm = midpoint voltage (1.4 v) 2 3 cv il cv ih 1 pci_sync_in vm vm
mpc8241 integrated processor hardware specifications, rev. 10 16 freescale semiconductor electrical and thermal characteristics register settings that define each dll mode are shown in table 9 . the dll_max_delay bit can lengthen the amount of time through the delay line by increasing the time between each of the 128 tap points in the delay lin e. although this increased time makes it easier to guarantee that the reference clock is within the dll lo ck range, there may be slightly more jitter in the output clock of the dll if the phase comparator shifts the clock between adjacent tap points. refer to the freescale application note an2164, mpc8245/mpc8241 memory clock design guidelines: part 1 , for details on dll modes and memory design. the value of the current tap point after the dll locks can be determined by reading bits 6?0 (dll_tap_count) of the dll tap count register (dtcr, located at offset 0xe3). these bits store the value (binary 0 through 127) of the current tap point and can indicate whether the dll advances or decrements as it maintains the dll lock. therefore, for evaluation purposes, dtcr can be read for all dll modes that support the t loop value used for the trace length of sdram_sync_out to sdram_sync_in. the dll mode with the smallest tap point value in the dtcr should be used because the bigger the tap point value, the more jitte r that can be expected for clock signals. keeping a dll mode locked below tap point decimal 12 is not recommended. table 9. dll mode definition dll mode bit 2 of configuration register at 0x76 bit 7 of configuration register at 0x72 normal tap delay, no dll extend 00 normal tap delay, dll extend 01 max tap delay, no dll extend 10 max tap delay, dll extend 11
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 17 electrical and thermal characteristics figure 7. dll locking range loop delay versus frequency of operation for dll_extend=0 and normal tap delay 23 10 15 20 0 25 30 1 t loop propagation delay time (ns) t clk sdram_sync_out period (ns) 27.5 22.5 17.5 12.5 7.5 4 5
mpc8241 integrated processor hardware specifications, rev. 10 18 freescale semiconductor electrical and thermal characteristics figure 8. dll locking range loop delay versus frequency of operation for dll_extend=1 and normal tap delay 23 10 15 20 0 25 30 1 t loop propagation delay time (ns) t clk sdram_sync_out period (ns) 27.5 22.5 17.5 12.5 7.5 4 5
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 19 electrical and thermal characteristics figure 9. dll locking range loop delay versus frequency of operation for dll_extend=0 and max tap delay 23 10 15 20 0 25 30 1 t loop propagation delay time (ns) t clk sdram_sync_out period (ns) 27.5 22.5 17.5 12.5 7.5 4 5
mpc8241 integrated processor hardware specifications, rev. 10 20 freescale semiconductor electrical and thermal characteristics figure 10. dll locking range loop delay versus frequency of operation for dll_extend=1 and max tap delay 4.5.2 input ac timing specifications table 10 provides the input ac timing specifications at recommended operating conditions (see table 2 ) with lv dd = 3.3 v 0.3 v. see figure 11 and figure 12 . table 10. input ac timing specifications num characteristic min max unit notes 10a pci input signals valid to pci_sync_in (input setup) 3.0 ? ns 1, 3 10b memory input signals valid to sys_logic_clk (input setup) 23 10 15 20 0 25 30 1 t loop propagation delay time (ns) t clk sdram_sync_out period (ns) 27.5 22.5 17.5 12.5 7.5 4 5
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 21 electrical and thermal characteristics 10b0 tap 0, register offset <0x77>, bits 5:4 = 0b00 2.6 ? ns 2, 3, 6 10b1 tap 1, register offset <0x77>, bits 5:4 = 0b01 1.9 ? 10b2 tap 2, register offset <0x77>, bits 5:4 = 0b10 (default) 1.2 ? 10b3 tap 3, register offset <0x77>, bits 5:4 = 0b11 0.5 ? 10c pic miscellaneous debug input signals valid to sys_logic_clk (input setup) 3.0 ? ns 2, 3 10d i 2 c input signals valid to sys_logic_clk (input setup) 3.0 ? ns 2, 3 10e mode select inputs valid to hrst_cpu /hrst_ctrl (input setup) 9 t clk ? ns 2, 3?5 11 t os ?sdram_sync_in to sys_logic_clk offset time 0.4 1.0 ns 7 11a sys_logic_clk to memory signal inputs invalid (input hold) 11a0 tap 0, register offset <0x77>, bits 5:4 = 0b00 0 ? ns 2, 3, 6 11a1 tap 1, register offset <0x77>, bits 5:4 = 0b01 0.7 ? 11a2 tap 2, register offset <0x77>, bits 5:4 = 0b10 (default) 1.4 ? 11a3 tap 3, register offset <0x77>, bits 5:4 = 0b11 2.1 ? 11b hrst_cpu /hrst_ctrl to mode select inputs invalid (input hold) 0 ? ns 2, 3, 5 11c pci_sync_in to inputs invalid (input hold) 1.0 ? ns 1, 2, 3 notes: 1. all pci signals are measured from gv dd _ov dd /2 of the rising edge of pci_sync_in to 0.4 gv dd _ov dd of the signal in question for 3.3-v pci signaling levels. see figure 12 . 2. all memory and related interface input signal specifications are measured from the ttl level (0.8 or 2.0 v) of the signal in question to the vm = 1.4 v of the rising edge of the memory bus clock. sys_logic_clk . sys_logic_clk is the same as pci_sync_in in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of pci_sync_in). see figure 11 . 3. input timings are measured at the pin. 4. t clk is the time of one sdram_sync_in clock cycle. 5. all mode select input signals specifications are measured from the ttl level (0.8 or 2.0 v) of the signal in question to the vm = 1.4 v of the rising edge of the hrst_cpu /hrst_ctrl signal. see figure 13 . 6. the memory interface input setup and hold times are programmable to four possible combinations by programming bits 5:4 of register offset <0x77> to select the desired input setup and hold times. 7. t os represents a timing adjustment for sdram_sync_in with respect to sys_logic_clk . due to the internal delay present on the sdram_sync_in signal with respect to the sys_logic_clk inputs to the dll, the resulting sdram clocks become offset by the delay amount. the feedback trace length of sdram_sync_out to sdram_sync_in must be shortened to accommodate this range relative to the sdram clock output trace lengths to maintain phase-alignment of the memory clocks with respect to sys_logic_clk . it is recommended that the length of sdram_sync_out to sdram_sync_in be shortened by 0.7 ns because that is the midpoint of the range of t os and allows the impact from the range of t os to be reduced. additional analyses of trace lengths and sdram loading must be performed to optimize timing. for details on trace measurements and the t os problem, refer to the freescale application note an2164, mpc8245/mpc8241 memory clock design guidelines . table 10. input ac timing specifications (continued) num characteristic min max unit notes
mpc8241 integrated processor hardware specifications, rev. 10 22 freescale semiconductor electrical and thermal characteristics figure 11. input/output timing diagram referenced to sdram_sync_in figure 12. input/output timing diagram referenced to pci_sync_in 11a vm = midpoint voltage (1.4 v). memory 10b-d inputs/outputs 13b 14b vm vm sdram_sync_in input timing output timing 12b-d 2.0 v 0.8 v 0.8 v 2.0 v t os 11a = input hold time of sdram_sync_in to memory. 12b-d = sys_logic_clk to output valid timing. 13b = output hold time for non-pci signals. 14b = sdram-sync_in to output high-impedance timing for non-pci signals. t os = offset timing required to align sys_logic_clk with sdram_sync_in. the sdram_sync_in signal sys_logic_clk vm pci_sync_in vm vm is adjusted by the dll to accommodate for internal delay. this causes sdram_sync_in to appear before sys_logic_clk once the dll locks. (after dll locks) shown in 2:1 mode notes: 10b-d = input signals valid timing. gv dd _ov dd 10a 11c pci_sync_in pci 12a 13a 14a gv dd _ov dd 0.285 input timing output timing inputs/outputs 2 gv dd _ov dd 2 gv dd _ov dd 2 0.4 x gv dd _ov dd x 0.615
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 23 electrical and thermal characteristics figure 13 shows the input timing diagram for mode select signals. figure 13. input timing diagram for mode select signals 4.5.3 output ac timing specification table 11 provides the processor bus ac timing specifications for the mpc8241 at recommended operating conditions (see table 2 ) with lv dd = 3.3 v 0.3 v (see figure 11 ). all output timings assume a purely resistive 50- load (see figure 14 ). output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the syst em. these specifications are for the default driver strengths that table 4 indicates. table 11. output ac timing specifications num characteristic min max unit notes 12a pci_sync_in to output valid, see figure 15 12a0 tap 0, pci_hold_del = 00, [mcp ,cke] = 11, 66 mhz pci (default) ? 6.0 ns 1, 3 12a1 tap 1, pci_hold_del = 01, [mcp ,cke] = 10 ? 6.5 12a2 tap 2, pci_hold_del = 10, [mcp ,cke] = 01, 33 mhz pci ? 7.0 12a3 tap 3, pci_hold_del = 11, [mcp ,cke] = 00 ? 7.5 12b sys_logic_clk to output valid (memory address, control, and data signals) ? 4.5 ns 2 12c sys_logic_clk to output valid (for all others) ? 7.0 ns 2 12d sys_logic_clk to output valid (for i 2 c) ? 5.0 ns 2 12e sys_logic_clk to output valid (rom/flash/port x) ? 6.0 ns 2 13a output hold (pci), see figure 15 13a0 tap 0, pci_hold_del = 00, [mcp ,cke] = 11, 66 mhz pci (default) 2.0 ? ns 1, 3, 4 13a1 tap 1, pci_hold_del = 01, [mcp ,cke] = 10 2.5 ? 13a2 tap 2, pci_hold_del = 10, [mcp ,cke] = 01, 33 mhz pci 3.0 ? 13a3 tap 3, pci_hold_del = 11, [mcp ,cke] = 00 3.5 ? 13b output hold (all others) 1.0 ? ns 2 14a pci_sync_in to output high impedance (for pci) ? 14.0 ns 1, 3 vm vm = midpoint voltage (1.4 v) 11b mode pins 10e hrst_cpu /hrst_ctrl 2.0 v 0.8 v
mpc8241 integrated processor hardware specifications, rev. 10 24 freescale semiconductor electrical and thermal characteristics figure 14 provides the ac test load for the mpc8241. figure 14. ac test load for the mpc8241 14b sys_logic_clk to output high impedance (for all others) ? 4.0 ns 2 notes: 1. all pci signals are measured from gv dd _ov dd /2 of the rising edge of pci_sync_in to 0.285 gv dd _ov dd or 0.615 gv dd _ov dd of the signal in question for 3.3 v pci signaling levels. see figure 12 . 2. all memory and related interface output signal specifications are specified from the vm = 1.4 v of the rising edge of the memory bus clock, sys_logic_clk to the ttl level (0.8 or 2.0 v) of the signal in question. sys_logic_clk is the same as pci_sync_in in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of pci_sync_in). see figure 11 . 3. pci bused signals are composed of the following signals: lock , irdy , c/be [3:0], par, trdy , frame , stop , devsel , perr , serr , ad[31:0], req [4:0], gnt [4:0], idsel , and inta . 4. to meet minimum output hold specifications relative to pci_sync_in for both 33- and 66-mhz pci systems, the mpc8241 has a programmable output hold delay for pci signals (the pci_sync_in to output valid timing is also affected). the initial value of the output hold delay is determined by the values on the mcp and cke reset configuration signals; the values on these two signals are inverted and subsequently stored as the initial settings of pci_hold_del = pmcr2[5, 4] (power management configuration register 2 <0x72>), respectively. because mcp and cke have internal pull-up resistors, the default value of pci_hold_del after reset is 0b00. additional output hold delay values are available by programming the pci_hold_del value of the pmcr2 configuration register. see figure 15 for pci_hold_del effect on output valid and hold time. table 11. output ac timing specifications (continued) num characteristic min max unit notes output z 0 = 50 gv dd _ov dd /2 for r l = 50 output measurements are made at the device pin pci or memory
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 25 electrical and thermal characteristics figure 15. pci_hold_del effect on output valid and hold time 4.6 i 2 c this section describes the dc and ac electrical characteristics for the i 2 c interfaces of the mpc8241. 4.6.1 i 2 c dc electrical characteristics table 12 provides the dc electrical characteristics for the i 2 c interfaces. table 12. i 2 c dc electrical characteristics at recommended operating conditions with ov dd of 3.3 v 5%. parameter symbol min max unit notes input high voltage level v ih 0.7 ov dd ov dd +0.3 v input low voltage level v il ?0.3 0.3 ov dd v low level output voltage v ol 00.2 ov dd v1 pci_sync_in pci inputs/outputs 33 mhz pci 12a2, 7.0 ns for 33 mhz pci pci_hold_del = 10 12a0, 6.0 ns for 66 mhz pci pci_hold_del = 00 13a2, 2.1 ns for 33 mhz pci pci_hold_del = 10 13a0, 1 ns for 66 mhz pci pci_hold_del = 00 output valid output hold note: diagram not to scale. as pci_hold_del values decrease pci inputs and outputs pci inputs/outputs 66 mhz pci pci_hold_del = 00 as pci_hold_del values increase ov dd /2 ov dd /2
mpc8241 integrated processor hardware specifications, rev. 10 26 freescale semiconductor electrical and thermal characteristics 4.6.2 i 2 c ac electrical specifications table 13 provides the ac timing parameters for the i 2 c interfaces. pulse width of spikes which must be suppressed by the input filter t i2khkl 050ns2 input current each i/o pin (input voltage is between 0.1 ov dd and 0.9 ov dd (max) i i ?10 10 a3 capacitance for each i/o pin c i ?10pf notes: 1. output voltage (open drain or open collector) condition = 3 ma sink current. 2. refer to the mpc8245 integrated processor reference manual for information on the digital filter used. 3. i/o pins obstruct the sda and scl lines if the ov dd is switched off. table 13. i 2 c ac electrical specifications all values refer to v ih (min) and v il (max) levels (see table 12 ). parameter symbol 1 min max unit scl clock frequency f i2c 0 400 khz low period of the scl clock t i2cl 4 1.3 ? s high period of the scl clock t i2ch 4 0.6 ? s setup time for a repeated start condition t i2svkh 4 0.6 ? s hold time (repeated) start condition (after this period, the first clock pulse is generated) t i2sxkl 4 0.6 ? s data setup time t i2dvkh 4 100 ? ns data input hold time: cbus compatible masters i 2 c bus devices t i2dxkl ? 0 2 ? ? s data output delay time: t i2ovkl ?0.9 3 set-up time for stop condition t i2pvkh 0.6 ? s bus free time between a stop and start condition t i2khdx 1.3 ? s noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ov dd ?v table 12. i 2 c dc electrical characteristics at recommended operating conditions with ov dd of 3.3 v 5%.
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 27 electrical and thermal characteristics figure 16 provides the ac test load for the i 2 c. figure 16. i 2 c ac test load noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ov dd ?v note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c timing (i2) for the time that the data with respect to the stop condition (p) reaching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the approp riate letter: r (rise) or f (fall). 2. as a transmitter, the mpc8245 provides a delay time of at least 300 ns for the sda signal (referred to the vihmin of the scl signal) to bridge the undefined region of the falling edge of scl to avoid the unintended generation of a start or stop condition. when the mpc8245 acts as the i 2 c bus master while transmitting, it drives both scl and sda. as long as the load on scl and sda is balanced, the mpc8245 does not cause an unintended generation of a start or stop condition. therefore, the 300 ns sda output delay time is not a concern. if, under some rare condition, the 300 ns sda output delay time is required for the mpc8245 as transmitter, the following setting is recommended for the fdr bit field of the i2cfdr register to ensure both the desired i 2 c scl clock frequency and sda output delay time are achieved. it is assumed that the desired i 2 c scl clock frequency is 400 khz and the digital filter sampling rate register (dffsr bits in i2cfdr) is programmed with its default setting of 0x10 (decimal 16): sdram clock frequency 100 mhz 133 mhz fdr bit setting 0x00 0x2a actual fdr divider selected 384 896 actual i 2 c scl frequency generated 260.4 khz 148.4 khz for details on i 2 c frequency calculation, refer to the application note an2919 ?determining the i 2 c frequency divider ratio for scl?. 3. the maximum t i2dxkl has only to be met if the device does not stretch the low period (t i2cl ) of the scl signal. 4. guaranteed by design table 13. i 2 c ac electrical specifications (continued) all values refer to v ih (min) and v il (max) levels (see table 12 ). parameter symbol 1 min max unit output z 0 = 50 ov dd /2 r l = 50
mpc8241 integrated processor hardware specifications, rev. 10 28 freescale semiconductor electrical and thermal characteristics figure 17 shows the ac timing diagram for the i 2 c bus. figure 17. i 2 c bus ac timing diagram 4.7 pic serial interrupt mode ac timing specifications table 14 provides the pic serial interrupt mode ac timing specifications for the mpc8241 at recommended operating conditions (see table 2 ) with gv dd _ov dd = 3.3 v 5% and lv dd = 3.3 v 0.3 v. table 14. pic serial interrupt mode ac timing specifications num characteristic min max unit notes 1 s_clk frequency 1/14 sdram_sync_in 1/2 sdram_sync_in mhz 1 2 s_clk duty cycle 40 60 % ? 3 s_clk output valid time ? 6 ns ? 4 output hold time 0 ? ns ? 5s_frame , s_rst output valid time ? 1 sys_logic_clk period + 6 ns 2 6 s_int input setup time to s_clk 1 sys_logic_clk period + 2 ? ns 2 7 s_int inputs invalid (hold time) to s_clk ? 0 ns 2 notes: 1. see the mpc8245 integrated processor reference manual for a description of the pic interrupt control register (icr) and s_clk frequency programming. 2. s_rst, s_frame , and s_int shown in figure 18 and figure 19 , depict timing relationships to sys_logic_clk and s_clk and do not describe functional relationships between s_rst, s_frame , and s_int. the mpc8245 integrated processor reference manual describes the functional relationships between these signals. 3. the sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral logic pll; sys_logic_clk is the same as sdram_sync_in when the sdram_sync_out to sdram_sync_in feedback loop is implemented and the dll is locked. see the mpc8245 integrated processor reference manual for a complete clocking description. sr s sda scl t i2cf t i2sxkl t i2cl t i2ch t i2dxkl, t i2ovkl t i2dvkh t i2sxkl t i2svkh t i2khkl t i2pvkh t i2cr t i2cf ps
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 29 electrical and thermal characteristics figure 18. pic serial interrupt mode output timing diagram figure 19. pic serial interrupt mode input timing diagram 4.7.1 ieee 1149.1 (jtag) ac timing specifications table 15 provides the jtag ac timing specifications for the mpc8241 while in the jtag operating mode at recommended operating conditions (see table 2 ) with lv dd = 3.3 v 0.3 v. timings are independent of the system clock (pci_sync_in). table 15. jtag ac timing specification (independent of pci_sync_in) num characteristic min max unit notes tck frequency of operation 0 25 mhz ? 1 tck cycle time 40 ? ns ? 2 tck clock pulse width measured at 1.5 v 20 ? ns ? 3 tck rise and fall times 0 3 ns ? 4trst setup time to tck falling edge 10 ? ns 1 5trst assert time 10 ? ns ? 6 input data setup time 5 ? ns 2 7 input data hold time 15 ? ns 2 8 tck to output data valid 0 30 ns 3 9 tck to output high impedance 0 30 ns 3 10 tms, tdi data setup time 5 ? ns ? s_clk s_rst vm vm vm s_frame sys_logic_clk vm vm vm vm 4 3 5 4 6 s_clk s_int 7 vm
mpc8241 integrated processor hardware specifications, rev. 10 30 freescale semiconductor electrical and thermal characteristics figure 20 through figure 23 show the different timing diagrams for jtag. figure 20. jtag clock input timing diagram figure 21. jtag trst timing diagram figure 22. jtag boundary scan timing diagram 11 tms, tdi data hold time 15 ? ns ? 12 tck to tdo data valid 0 15 ns ? 13 tck to tdo high impedance 0 15 ns ? notes: 1. trst is an asynchronous signal. the setup time is for test purposes only. 2. nontest (other than tdi and tms) signal input timing with respect to tck. 3. nontest (other than tdo) signal output timing with respect to tck. table 15. jtag ac timing specification (independent of pci_sync_in) num characteristic min max unit notes tck 2 2 1 vm vm vm 3 3 vm = midpoint voltage 4 5 trst tck 6 7 input data valid 8 9 output data valid tck data inputs data outputs data outputs
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 31 package description figure 23. test access port timing diagram 5 package description this section details package paramete rs, pin assignments, and dimensions. 5.1 package parameters for the mpc8241 the mpc8241 uses a 25 mm 25 mm, cavity up, 357-pin plastic ball grid array (pbga) package. the package parameters are as follows. package outline 25 mm 25 mm interconnects 357 pitch 1.27 mm solder balls zp (pbga)?62 sn/36 pb/2 ag?available only in rev b parts zq (thick substrate thick mold cap pbga)?62 sn/36 pb/2 ag vr (lead free version of package)?95.5 sn/4.0 ag/0.5 cu solder ball diameter 0.75 mm maximum module height 2.52 mm co-planarity specification 0.15 mm maximum force 6.0 lbs. total, uniformly distributed over package (8 grams/ball) 10 11 input data valid 12 13 output data valid tck tdi, tms tdo tdo
mpc8241 integrated processor hardware specifications, rev. 10 32 freescale semiconductor package description 5.2 pin assignments and package dimensions figure 24 shows the top surface, side profile, and pinout of the mpc8241, 357 pbga zp package. note that this is available for rev. b parts only. figure 24. mpc8241 package dimensions and pinout assignments (zp package) w v u t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 side view bottom view 18x 4x 357x b top view a2 a3 e 0.30 m c d a a1 d2 0.15 m c e e2 0.20 c a b 0.2 d1 e1 ab 0.25 c 0.35 c c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b is the maximum solder ball diameter measured parallel to datum c. dim min max millimeters a --- 2.05 a1 0.50 0.70 a2 0.95 1.35 a3 0.70 0.90 b 0.60 0.90 d 25.00 bsc d1 22.86 bsc d2 22.40 22.60 e 1.27 bsc e 25.00 bsc e1 22.86 bsc e2 22.40 22.60
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 33 package description figure 25 shows the top surface, side profile, and pinout of the mpc8241, 357 pbga zq and vr packages. figure 25. mpc8241 package dimensions and pinout assignments (zq and vr packages)
mpc8241 integrated processor hardware specifications, rev. 10 34 freescale semiconductor package description 5.3 pinout listings table 16 provides the pinout listing for the mpc8241, 357 pbga package. table 16. mpc8241 pinout listing signal name package pin number pin type power supply output driver type notes pci interface signals c/be [3:0] v11 v7 w3 r3 i/o gv dd _ov dd drv_pci 1, 2 devsel u6 i/o gv dd _ov dd drv_pci 2, 3 frame t8 i/o gv dd _ov dd drv_pci 2, 3 irdy u7 i/o gv dd _ov dd drv_pci 2, 3 lock v6 input gv dd _ov dd ?3 ad[31:0] u13 v13 u11 w14 v14 u12 w10 t10 v10 u9 v9 w9 w8 t9 w7 v8 v4 w4 v3 v2 t5 r6 v1 t2 u3 p3 t4 r1 t3 r4 u2 u1 i/o gv dd _ov dd drv_pci 1, 2 pa r r 7 i / o g v dd _ov dd drv_pci 2 gnt [3:0] w15 u15 w17 v12 output gv dd _ov dd drv_pci 1, 2 gnt4 /da5 t11 output gv dd _ov dd drv_pci 2, 4, 5 req [3:0] v16 u14 t15 v15 input gv dd _ov dd ?1, 6 req4 /da4 w13 i/o gv dd _ov dd ?5, 6 perr t7 i/o gv dd _ov dd drv_pci 2, 3, 7 serr u5 i/o gv dd _ov dd drv_pci 2, 3, 8 stop w5 i/o gv dd _ov dd drv_pci 2, 3 trdy w6 i/o gv dd _ov dd drv_pci 2, 3 inta t12 output gv dd _ov dd drv_pci 2, 8 idsel u10 input gv dd _ov dd ?? memory interface signals mdl[0:31] m19 m17 l16 l17 k18 j18 k17 k16 j15 j17 h18 f16 h16 h15 g17 d19 b3 c4 c2 d3 g5 e1 h5 e2 f1 f2 g2 j5 h1 h4 j4 j1 i/o gv dd _ov dd drv_std_mem 1, 9 mdh[0:31] m18 l18 l15 k19 k15 j19 j16 h17 g19 g18 g16 d18 f18 e18 g15 e15 c3 d4 e5 f5 d1 e4 d2 e3 f4 g3 g4 g1 h2 j3 j2 k5 i/o gv dd _ov dd drv_std_mem 1 dqm[0:7] a18 b18 a6 c7 d15 d14 a9 b8 output gv dd _ov dd drv_mem_ctrl 1 cs [0:7] a17 b17 c16 c17 c9 c8 a10 b10 output gv dd _ov dd drv_mem_ctrl 1 foe a7 i/o gv dd _ov dd drv_mem_ctrl 10, 11 rcs0 c10 output gv dd _ov dd drv_mem_ctrl 10, 11
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 35 package description rcs1 b9 output gv dd _ov dd drv_mem_ctrl ? rcs2 /trig_in p18 i/o gv dd _ov dd ?5, 12 rcs3 /trig_out n18 output gv dd _ov dd drv_std_mem 5 sdma[1:0] a15 b15 i/o gv dd _ov dd drv_mem_ctrl 1, 10, 11 sdma[11:2] a11 b12 a12 c12 b13 c13 d12 a14 c14 b14 output gv dd _ov dd drv_mem_ctrl 1 drdy p1 input gv dd _ov dd ?12, 13 sdma12/sreset l3 i/o gv dd _ov dd drv_mem_ctrl 5, 12 sdma13/tben k3 i/o gv dd _ov dd drv_mem_ctrl 5, 12 sdma14/chkstop_in k2 i/o gv dd _ov dd drv_mem_ctrl 5, 12 sdba1 c11 output gv dd _ov dd drv_mem_ctrl ? sdba0 b11 output gv dd _ov dd drv_mem_ctrl ? par[0:7] e19 c19 d5 d6 e16 f17 b2 c1 i/o gv dd _ov dd drv_std_mem 1 sdras b19 output gv dd _ov dd drv_mem_ctrl 10 sdcas d16 output gv dd _ov dd drv_mem_ctrl 10 cke c6 output gv dd _ov dd drv_mem_ctrl 10, 11 we b16 output gv dd _ov dd drv_mem_ctrl ? as a16 output gv dd _ov dd drv_mem_ctrl 10, 11 pic control signals irq0/s_int p4 input gv dd _ov dd ?? irq1/s_clk r2 i/o gv dd _ov dd drv_pci ? irq2/s_rst u19 i/o gv dd _ov dd drv_pci ? irq3/s_frame p15 i/o gv dd _ov dd drv_pci ? irq4/l_int p2 i/o gv dd _ov dd drv_pci ? i 2 c control signals sda p17 i/o gv dd _ov dd drv_std_mem 8, 12 scl r19 i/o gv dd _ov dd drv_std_mem 8, 12 duart control signals sout1/pci_clk0 t16 output gv dd _ov dd drv_mem_ctrl 5, 14 sin1/pci_clk1 u16 i/o gv dd _ov dd drv_mem_ctrl 5, 14, 24 sout2/rts1 /pci_clk2 w18 output gv dd _ov dd drv_mem_ctrl 5, 14 sin2/cts1 /pci_clk3 v19 i gv dd _ov dd drv_mem_ctrl 5, 14, 24 clock-out signals pci_clk0/sout1 t16 output gv dd _ov dd drv_pci_clk 5, 14 table 16. mpc8241 pinout listing (continued) signal name package pin number pin type power supply output driver type notes
mpc8241 integrated processor hardware specifications, rev. 10 36 freescale semiconductor package description pci_clk1/sin1 u16 output gv dd _ov dd drv_pci_clk 5, 14, 24 pci_clk2/rts1 /sout2 w18 output gv dd _ov dd drv_pci_clk 5, 14 pci_clk3/cts1 /sin2 v19 output gv dd _ov dd drv_pci_clk 5, 14, 24 pci_clk4/da3 v17 output gv dd _ov dd drv_pci_clk 5, 14 pci_sync_out u17 output gv dd _ov dd drv_pci_clk ? pci_sync_in v18 input gv dd _ov dd ?? sdram_clk[0:3] d7 b7 c5 a5 output gv dd _ov dd drv_mem_ctrl 1, 22 sdram_sync_out b4 output gv dd _ov dd drv_mem_ctrl ? sdram_sync_in a4 input gv dd _ov dd ?? cko/da1 l1 output gv dd _ov dd drv_std_mem 5 osc_in r17 input gv dd _ov dd ?15 miscellaneous signals hrst_ctrl m2 input gv dd _ov dd ?25 hrst_cpu l4 input gv dd _ov dd ?25 mcp k4 output gv dd _ov dd drv_std_mem 10, 11, 16 nmi m1 input gv dd _ov dd ?? smi l2 input gv dd _ov dd ?12 sreset /sdma12 l3 i/o gv dd _ov dd drv_mem_ctrl 5, 12 tben/sdma13 k3 i/o gv dd _ov dd drv_mem_ctrl 5, 12 qack /da0 a3 output gv dd _ov dd drv_std_mem 5, 11, 12 chkstop_in /sdma14 k2 i/o gv dd _ov dd drv_mem_ctrl 5, 12 trig_in/rcs2 p18 i/o gv dd _ov dd ?5, 12 trig_out/rcs3 n18 output gv dd _ov dd drv_std_mem 5 maa[0:2] e17 d17 c18 output gv dd _ov dd drv_std_mem 1, 10, 11 miv k1 output gv dd _ov dd drv_std_mem 23 pmaa[0:1] n19 n17 output gv dd _ov dd drv_std_mem 1, 2, 10, 11 pmaa[2] m15 output gv dd _ov dd drv_std_mem 1, 2, 10, 11 test/configuration signals pll_cfg[0:4]/da[10:6] n3 n2 n1 m4 m3 i/o gv dd _ov dd ? 1, 5, 20 test0 p16 input gv dd _ov dd ?13, 21 rtc d13 input gv dd _ov dd ?12 tck t19 input gv dd _ov dd ?6, 13 tdi n15 input gv dd _ov dd ?6, 13 tdo t17 output gv dd _ov dd drv_pci 23 table 16. mpc8241 pinout listing (continued) signal name package pin number pin type power supply output driver type notes
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 37 package description tms t18 input gv dd _ov dd ?6, 13 trst r16 input gv dd _ov dd ?6, 13 power and ground signals gndring/gnd f07 f08 f09 f10 f11 f12 f13 g07 g08 g09 g10 g11 g12 g13 h07 h08 h09 h10 h11 h12 h13 j07 j08 j09 j10 j11 j12 j13 k07 k08 k09 k10 k11 k12 k13 l07 l08 l09 l10 l11 l12 l13 m07 m08 m09 m10 m11 m12 m13 n07 n08 n09 n10 n11 n12 n13 p08 p09 p10 p11 p12 p13 r15 ground ? ? 17 lv dd r18 u18 t1 u4 t6 w11 t14 reference voltage 3.3 v, 5.0 v lv dd ?? gv dd _ov dd /pwrring d09 d10 d11 e06 e07 e08 e09 e10 e11 e12 e13 e14 f06 f14 g06 g14 h06 h14 j06 j14 k06 k14 l06 l14 m06 m14 n06 n14 p06 p07 p14 r08 r09 r10 r11 r12 power for memory drivers and pci/stnd 3.3 v gv dd _ov dd ?18 v dd f03 h3 l5 n4 p5 v5 u8 w12 w16 r13 p19 l19 h19 f19 f15 c15 a13 a8 b5 a2 power for core 1.8 v v dd ?? no connect n5 w2 b1 ? ? ? ? av dd m5 power for pll (cpu core logic) 1.8 v av dd ?? av dd 2r14 power for pll (peripheral logic) 1.8 v av dd 2?? debug/manufacturing pins da0/qack a3 output gv dd _ov dd drv_std_mem 5, 11, 12 da1/cko l1 output gv dd _ov dd drv_std_mem 5 da2 r5 output gv dd _ov dd drv_pci 19 da3/pci_clk4 v17 output gv dd _ov dd drv_pci_clk 5 da4/req4 w13 i/o gv dd _ov dd ?5, 6 da5/gnt4 t11 output gv dd _ov dd drv_pci 2, 4, 5 table 16. mpc8241 pinout listing (continued) signal name package pin number pin type power supply output driver type notes
mpc8241 integrated processor hardware specifications, rev. 10 38 freescale semiconductor package description da[10:6]/ pll_cfg[0:4] n3 n2 n1 m4 m3 i/o gv dd _ov dd ? 1, 5, 20 da[11] t13 output gv dd _ov dd drv_pci 1, 19 da[12:13] m16 n16 output gv dd _ov dd drv_std_mem 19 da[14:15] b6 d8 output gv dd _ov dd drv_mem_ctrl 1, 19 notes: 1. multi-pin signals such as ad[31:0] or mdl[0:31] physical package pin numbers are listed in order corresponding to the signal names. ex: ad0 is on pin u1, ad1 is on pin u2,..., ad31 is on pin u13. 2. this pin is affected by a programmable pci_hold_del parameter. 3. a weak pull-up resistor (2?10 k ) should be placed on this pci control pin to lv dd . 4. gnt4 is a reset configuration pin with an internal pull-up resistor that is enabled only when in the reset state. 5. this pin is a multiplexed signal and appears more than once in this table. 6. this pin has an internal pull-up resistor that is enabled at all times. the value of the internal pull-up resistor is not gua ranteed, but is sufficient to prevent unused inputs from floating. 7. this pin is a sustained three-state pin as defined by the pci local bus specification (rev. 2.2). 8. this pin is an open-drain signal. 9. dl[0] is a reset configuration pin with an internal pull-up resistor that is enabled only when in the reset state. the value of the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic 1 is read into configuration bits during r eset. 10.this pin has an internal pull-up resistor that is enabled only when in the reset state. the value of the internal pull-up re sistor is not guaranteed, but is sufficient to ensure that a logic 1 is read into configuration bits during reset. 11.this pin is a reset configuration pin. 12.a weak pull-up resistor (2?10 k ) should be placed on this pin to gv dd _ov dd . 13.v ih and v il for these signals are the same as the pci v ih and v il entries in ta b l e 3 . 14.external pci clocking source or fanout buffer may be required for system if using the mpc8241 duart functionality because pci_clk[0:3] are not available in duart mode. only pci_clk4 is available in duart mode. 15.osc_in uses the 3.3-v pci interface driver, which is 5-v tolerant. see ta b l e 2 for details. 16.this pin can be programmed as driven (default) or as open-drain (in miocr 1). 17.all grounded pins are connected together. connections should not be made to individual pins. the list represents the balls that are connected to ground. 18.gv dd _ov dd must not exceed v dd /av dd /av dd 2 by more than 1.8 v at any time including during power-on reset. note that gv dd _ov dd pins are all shorted together, pwrring. the list represents the balls that are connected to pwrring. connections should not be made to individual pwrring pins. 19.treat these pins as no connects unless debug address functionality is used. 20.pll_cfg signals must be driven on reset and must be held for at least 25 clock cycles after the negation of hrst_ctrl and hrst_cpu in order to be latched. 21.place a pull-up resistor of 120 or less on the test0 pin. 22.sdram_clk[0:3] and sdram_sync_out signals use drv_mem_ctrl for chip rev. 1.1 (a). these signals use drv_mem_clk for chip rev. 1.2b. 23.the driver capability of this pin is hardwired to 40 and cannot be changed. 24.freescale typically expects that customers using the serial port will have sufficient drivers available in the rs232 transce iver to drive the cts pin actively as an input if they are using that mode. no pullups would be needed in these circumstances. 25. hrst_cpu /hrst_ctrl must transition from a logic 0 to a logic 1 in less than one sdram_sync_in clock cycle for the device to be in the nonreset state table 16. mpc8241 pinout listing (continued) signal name package pin number pin type power supply output driver type notes
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 39 pll configuration 6 pll configuration the pll_cfg[0:4] are configured by the internal plls. for a specific pci_sync_in (pci bus) frequency, the pll configuration signals set both the peripheral logic/memory bus pll (vco) frequency of operation for the pci-to-memory frequency multiplying and the mpc603e cpu pll (vco) frequency of operation for memory-to-cpu frequency multiplying. the pll configurations are shown in table 17 and table 18 . table 17. pll configurations (166- and 200-mhz) ref 2 pll_cfg [0:4] 1 166 mhz-part 2 200-mhz part 2 multipliers pci clock input (pci_ sync_in) range 3 (mhz) peripheral logic/ mem bus clock range (mhz) cpu clock range (mhz) pci clock input (pci_ sync_in) range 3 (mhz) peripheral logic/ mem bus clock range (mhz) cpu clock range (mhz) pci-to- mem (mem vco) mem-to- cpu (cpu vco) 0 00000 not available 25-26 5 75-78 188-195 3 (2) 2.5 (2) 2 00010 34 4 ?37 5 34?37 153?166 34 4 ?44 5 34?44 153?200 1 (4) 4.5 (2) 3 00011 6 50 7 ?66 3 50?66 100?132 50 7 ?66 3 50?66 100?132 1 (bypass) 2 (4) 4 00100 25?41 5 50?82 100?164 25?44 8,10 50?88 100?176 2 (4) 2 (4) 6 00110 9 bypass bypass bypass bypass 7 rev. b 00111 6 50 4 ?55 5 50?55 150?166 50 4 ?66 3 50?66 150?198 1 (bypass) 3 (2) 7 rev. d 00111 not available 8 01000 50 4 ?55 5 50?55 150?166 50 4 ?66 3 50?66 150?198 1 (4) 3 (2) 9 01001 38 4 ?41 5,11 76?82 152?164 38 4 ?50 5,12 76?100 152?200 2 (2) 2 (2) b 01011 not available 44 5 66 198 2(2) 2.5(2) c 01100 30 4 ?33 5 60?66 150?165 30 4 ?40 5 60?80 150?200 2 (4) 2.5 (2) e 01110 25?27 5 50?54 150?162 25?33 5 60?66 150?198 2 (4) 3 (2) 10 10000 25?27 5,11 75?83 150?166 25?33 5,12 75?100 150?200 3 (2) 2 (2) 12 10010 50 4 ?55 5,11 75?83 150?166 50 4 ?66 3 75?99 150?198 1.5 (2) 2 (2) 14 10100 not available 25?28 5 50?56 175?196 2 (4) 3.5 (2) 16 10110 25 5 50 200 2(4) 4(2) 17 10111 25 5 100 200 4(2) 2(2) 19 11001 33 5,13 66 165 33 13 ?40 5 66?80 165?200 2(2) 2.5(2) 1a 11010 37 4 ?41 5 37?41 150?166 37 4 ?50 5 37?50 150?200 1 (4) 4 (2) 1b 11011 not available 33 5,13 66 198 2(2) 3(2) 1c 11100 44 5,13 66 198 1.5(2) 3(2) 1d 11101 44 5,13 66 166 44 13 ?53 5 66?80 165?200 1.5 (2) 2.5 (2)
mpc8241 integrated processor hardware specifications, rev. 10 40 freescale semiconductor pll configuration 1e 11110 14 not usable not usable off off 1f 11111 14 not usable not usable off off notes: 1. pll_cfg[0:4] settings not listed are reserved. bits 7?4 of register offset <0xe2> contain the pll_cfg[0:4] setting value. note the impact of the relevant revisions for mode 7. 2. range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity. 3. limited by maximum pci input frequency (66 mhz). 4. limited by minimum cpu vco frequency (300 mhz). 5. limited by maximum cpu operating frequency. 6. in pll bypass mode, the pci_sync_in input signal clocks the internal processor directly, the peripheral logic pll is disabled, and the bus mode is set for 1:1 (pci:mem) mode operation. this mode is intended for hardware modeling. the ac timing specifications in this document do not apply in pll bypass mode. 7. limited by minimum cpu operating frequency (100 mhz). 8. limited due to maximum memory vco frequency (352 mhz). 9. in dual pll bypass mode, the pci_sync_in input signal clocks the internal peripheral logic directly, the peripheral logic pll is disabled, and the bus mode is set for 1:1 (pci_sync_in:mem) mode operation. in this mode, the osc_in input signal clocks the internal processor directly in 1:1 (osc_in:cpu) mode operation, and the processor pll is disabled. the pci_sync_in and osc_in input clocks must be externally synchronized. this mode is intended for hardware modeling. the ac timing specifications in this document do not apply in dual pll bypass mode. 10.limited by maximum cpu vco frequency (704 mhz). 11.limited by maximum system memory interface operating frequency (83 mhz @ 166 mhz cpu bus speed). 12.limited by maximum system memory interface operating frequency (100 mhz @ 200 mhz cpu bus speed). 13.limited by minimum memory vco frequency (132 mhz). 14.in clock off mode, no clocking occurs inside the mpc8241, regardless of the pci_sync_in input. table 18. pll configurations (266-mhz parts) ref 2 pll_ cfg[0:4] 10,11 266-mhz part 9 multipliers pci clock input (pci_sync_in) range 1 (mhz) periph logic/ mem bus clock range (mhz) cpu clock range (mhz) pci-to-mem (mem vco) mem-to-cpu (cpu vco) 0 00000 25?35 5 75?105 188?263 3 (2) 2.5 (2) 1 00001 25?29 5 75?88 225?264 3 (2) 3 (2) 2 00010 50 15 ?59 5 50?59 225?266 1 (4) 4.5 (2) 3 00011 12 50 14 ?66 1 50?66 100?133 1 (bypass) 2 (4) 4 00100 25?44 4 50?88 100?176 2 (4) 2 (4) table 17. pll configurations (166- and 200-mhz) (continued) ref 2 pll_cfg [0:4] 1 166 mhz-part 2 200-mhz part 2 multipliers pci clock input (pci_ sync_in) range 3 (mhz) peripheral logic/ mem bus clock range (mhz) cpu clock range (mhz) pci clock input (pci_ sync_in) range 3 (mhz) peripheral logic/ mem bus clock range (mhz) cpu clock range (mhz) pci-to- mem (mem vco) mem-to- cpu (cpu vco)
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 41 pll configuration 6 00110 13 bypass bypass 7 (rev. b) 00111 12 50 6 ?66 1 50?66 150?198 1 (bypass) 3 (2) 7 (rev. d) 00111 14 not available 8 01000 50 6 ?66 1 50?66 150?198 1 (4) 3 (2) 9 01001 38 6 ?66 1 76?132 152?264 2 (2) 2 (2) a 01010 25?29 5 50?58 225?261 2 (4) 4.5 (2) b 01011 45 3 ?59 5 68?88 204?264 1.5 (2) 3 (2) c 01100 30 6 ?44 4 60?88 150?220 2 (4) 2.5 (2) d 01101 45 3 ?50 5 68?75 238?263 1.5 (2) 3.5 (2) e 01110 25?44 5 50?88 150?264 2 (4) 3 (2) f 01111 25 5 75 263 3 (2) 3.5 (2) 10 10000 25?44 5 75?132 150?264 3 (2) 2 (2) 11 10001 25?26 5 100?106 250?266 4 (2) 2.5 (2) 12 10010 50 6 ?66 1 75?99 150?198 1.5 (2) 2 (2) 13 10011 not available 4 (2) 3 (2) 14 10100 25?38 5 50?76 175?266 2 (4) 3.5 (2) 15 10101 not available 2.5 (2) 4 (2) 16 10110 25?33 5 50?66 200?264 2 (4) 4 (2) 17 10111 25?33 5 100?132 200?264 4 (2) 2 (2) 18 11000 27 3 ?35 5 68?88 204?264 2.5 (2) 3 (2) 19 11001 33 3 ?53 5 66?106 165?265 2 (2) 2.5 (2) 1a 11010 50 18 ?66 1 50?66 200?264 1 (4) 4 (2) 1b 11011 34 3 ?44 5 68?88 204?264 2 (2) 3 (2) 1c 11100 44 3 ?59 5 66?88 198?264 1.5 (2) 3 (2) 1d 11101 44 3 ?66 1 66?99 165?248 1.5 (2) 2.5 (2) 1e (rev. b) 11110 8 not usable off off 1e (rev. d) 11110 33 3 -38 5 66-76 231-266 2(2) 3.5(2) table 18. pll configurations (266-mhz parts) (continued) ref 2 pll_ cfg[0:4] 10,11 266-mhz part 9 multipliers pci clock input (pci_sync_in) range 1 (mhz) periph logic/ mem bus clock range (mhz) cpu clock range (mhz) pci-to-mem (mem vco) mem-to-cpu (cpu vco)
mpc8241 integrated processor hardware specifications, rev. 10 42 freescale semiconductor system design information 7 system design information this section provides electrical and thermal design recommendations for successful application of the mpc8241. 7.1 pll power supply filtering the av dd and av dd 2 power signals on the mpc8241 provide power to the peripheral logic/memory bus pll and the mpc603e processor pll. to ensure stability of the internal clocks, the power supplied to the av dd and av dd 2 input signals should be filtered of any noise in the 500 khz to 10 mhz resonant frequency range of the plls. two separate circuits similar to the one shown in figure 26 using surface mount capacitors with minimum effective series inductance (esl) is recommended for av dd and av dd 2 power signal pins. in high speed digital design: a handbook of black magic (prentice hall, 1993), dr. howard johnson recommends using multiple small capac itors of equal value instead of multiple values. 1f 11111 8 not usable off off notes: 1. limited by maximum pci input frequency (66 mhz). 2. note the impact of the relevant revisions for modes 7 and 1e. 3. limited by minimum memory vco frequency (132 mhz). 4. limited due to maximum memory vco frequency (352 mhz). 5. limited by maximum cpu operating frequency. 6. limited by minimum cpu vco frequency (300 mhz). 7. limited by maximum cpu vco frequency (704 mhz). 8. in clock off mode, no clocking occurs inside the mpc8241, regardless of the pci_sync_in input. 9. range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity. 10.pll_cfg[0:4] settings that are not listed are reserved. 11.bits 7?4 of register offset <0xe2> contain the pll_cfg[0:4] setting value. 12.in pll bypass mode, the pci_sync_in input signal clocks the internal processor directly, the peripheral logic pll is disabled, and the bus mode is set for 1:1 (pci:mem) mode operation. this mode is intended for hardware modeling. the ac timing specifications in this document do not apply in pll bypass mode. 13.in dual pll bypass mode, the pci_sync_in input signal clocks the internal peripheral logic directly, the peripheral logic pll is disabled, and the bus mode is set for 1:1 (pci_sync_in:mem) mode operation. in this mode, the osc_in input signal clocks the internal processor directly in 1:1 (osc_in:cpu) mode operation and the processor pll is disabled. the pci_sync_in and osc_in input clocks must be externally synchronized. this mode is intended for hardware modeling. the ac timing specifications in this document do not apply in dual pll bypass mode. 14.limited by minimum cpu operating frequency (100 mhz). 15.limited by minimum memory bus frequency (50 mhz). table 18. pll configurations (266-mhz parts) (continued) ref 2 pll_ cfg[0:4] 10,11 266-mhz part 9 multipliers pci clock input (pci_sync_in) range 1 (mhz) periph logic/ mem bus clock range (mhz) cpu clock range (mhz) pci-to-mem (mem vco) mem-to-cpu (cpu vco)
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 43 system design information place the circuits as closely as possible to the respective input signal pins to minimize noise coupled from nearby circuits. routing from the capacitors to the input signal pins should be as direct as possible with minimal inductance of vias. figure 26. pll power supply filter circuit 7.2 decoupling recommendations dynamic power management, large a ddress and data buses, and high op erating frequencies enable the mpc8241 to generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the mpc8241 system, and the mpc8241 itself requires a clean, tightly regulated source of power. therefore, place at least one decoupling capacitor at each v dd , gv dd _ov dd , and lv dd pin. these decoupling capacitors receive their power from dedicated power planes in the pcb, using short traces to minimize inductance. these capacitors should have a value of 0.1 f. to minimize lead inductance, use only ceramic smt (surface mount technology) capacitors, preferably 0508 or 0603, on which connections are made along the length of the part. in addition, distribute several bulk storage capacitors around the pcb to feed the v dd , gv dd _ov dd , and lv dd planes and enable quick recharging of the sma ller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the necessary quick response time, and should be connected to the power and ground planes through two vias to minimize inductance. freescale recommends using bulk capacitors: 100?330 f (avx tps tantalum or sanyo oscon). 7.3 connection recommendations to ensure reliable operation, connect unused inputs to an appropriate signal level. tie unused active-low inputs to ov dd . connect unused active-high inputs to gnd. all no connect (nc) signals must remain unconnected. power and ground connections must be made to all external v dd , gv dd _ov dd , lv dd , and gnd pins. the pci_sync_out signal is to be routed halfway out to the pci devices and then returned to the pci_sync_in input. the sdram_sync_out signal is to be routed halfway out to the sdram devices and then returned to the sdram_sync_in input of the mpc8241. the trace length can be used to skew or adjust the timing window as needed. see the tundra tsi107? design guide (an1849) and freescale application notes an2164/d, mpc8245/mpc8241 memory clock design guidelines: part 1 and an2746, mpc8245/mpc8241 memory clock design guidelines: part 2 for more details. note the sdram_sync_in to pci_sync_in time requirement (see table 10 ). v dd av dd or av dd 2 2.2 f 2.2 f gnd low esl surface mount capacitors 10
mpc8241 integrated processor hardware specifications, rev. 10 44 freescale semiconductor system design information 7.4 pull-up/pull-down resistor requirements the data bus input receivers are normally turned off wh en no read operation is in progress; therefore, they do not require pull-up resistors on the bus. the data bus signals are: mdh[0:31], mdl[0:31], and par[0:7]. if the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (mdl[0:31] and par[4:7]) are disabled, and their outputs drive logi c zeros when they would otherwise be driven. for this mode, these pins do not require pull-up resistors and should be left unconnected to minimize possible output switching. the test0 pin requires a pull-up resistor of 120 or less connected to gv dd _ov dd . rtc should have weak pull-up resistors (2?10 k ) connected to gv dd _ov dd and that the following signals should be pulled up to gv dd _ov dd with weak pull-up resistors (2?10 k ): sda, scl, smi , sreset /sdma12, tben/sdma13, chkstop_in /sdma14, trig_in/rcs2 , qack /da0, and drdy . the following pci control signals should be pulled up to lv dd (the clamping voltage) with weak pull-up resistors (2?10 k ): devsel , frame , irdy , lock , perr , serr , stop , and trdy . the resistor values may need to have stronger adjustment to reduce induced noise on specific board designs. the following pins have internal pull-up resistors enabled at all times: req [3:0], req4 /da4, tck, tdi, tms, and trst . see table 16 . the following pins have internal pull-up resistors that are enabled only while the device is in the reset state: gnt4 /da5, mdl0, foe , rcs0 , sdras , sdcas , cke, as , mcp , maa[0:2], and pmaa[0:2]. see table 16 . the following pins are reset configuration pins: gnt4 /da5, mdl[0], foe , rcs0 , cke, as , mcp , qack /da0, maa[0:2], pmaa[0:2], sdma[1:0], mdh[16:31], and pll_cfg[0:4]/da[10:15]. these pins are sampled during reset to configure the device. the pll_cfg[0:4] signals are sampled a few clocks after the negation of hrst_cpu and hrst_ctrl . reset configuration pins should be tied to gnd by means of 1-k pull-down resistors to ensure that a logic zero level is read into the configuration bits during reset if the default logic-one level is not desired. any other unused active low input pins should be tied to a logic-one level by means of weak pull-up resistors (2?10 k ) to the appropriate power supply listed in table 16 . unused active high input pins should be tied to gnd by means of weak pull-down resistors (2?10 k ). 7.5 pci reference voltage?lv dd the mpc8241 pci reference voltage (lv dd ) pins should be connected to 3.3 0.3 v power supply if interfacing the mpc8241 into a 3.3-v pci bus system. similarly, the lv dd pins should be connected to 5.0 v 5% power supply if interfacing the mpc8241 into a 5-v pci bus system. for either reference voltage, the mpc8241 always performs 3.3-v signaling as described in the pci local bus specification (rev. 2.2). the mpc8241 tolerates 5-v signals when interfaced into a 5-v pci bus system. (see errata no. 18 in the mpc8245/mpc8241 integrated processor chip errata ) .
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 45 system design information 7.6 jtag configuration signals boundary scan testing is enabled through the jtag interface signals. the trst signal is optional in the ieee 1149.1 specification, but is provided on all pro cessors that implement the powerpc architecture. while the tap controller can be forced to the reset state using only the tck and tms signals, more reliable power-on reset performance will be obtained if the trst signal is asserted during power-on reset. because the jtag interface is also used for accessing the common on-chip processor (cop) function, simply tying trst to hreset is not practical. the cop function of these processors allows a remote computer system (typically, a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop interface connects primarily through the jtag port, with additional status monitoring signals. the cop port must independently assert h reset or trst to control the processor. if the target system has independent reset sources, such as voltage m onitors, watchdog timers, power supply failures, or push-button switches, the cop reset signals must be merged into these signals with logic. the arrangement shown in figure 27 allows the cop port to independently assert hreset or trst , while ensuring that the target can drive hreset as well. if the jtag interface and cop header will not be used, trst should be tied to hreset through a 0- isolation resistor so that it is asserted when the system reset signal (hreset ) is asserted, ensuring that the jtag scan chain is initialized during power-on. although freescale recommends that the cop header be designed into the system as shown in figure 27 , if this is not possible, the isolation resistor will allow future access to trst in the case where a jtag interface may need to be wired onto the system in debug situations. the cop interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a berg header). typically, pin 14 is removed as a connector key. there is no standardized way to number the cop header shown in figure 27 . consequently, different emulator vendors number the pins differently. some pins are numbered top-to-bottom and left-to-right while others use left-to-right then top-to-bottom a nd still others number the pins counter clockwise from pin 1 (as with an ic). regardless of the numbering, the signal placement recommended in figure 27 is common to all known emulators.
mpc8241 integrated processor hardware specifications, rev. 10 46 freescale semiconductor system design information figure 27. cop connector diagram hreset 7 hrst_cpu hrst_ctrl from target board sources hreset 13 sreset 5 sreset 5 sreset 5 nc nc nc 11 vdd_sense 6 5 2 15 3 1 k 10 k 10 k 10 k ov dd ov dd ov dd ov dd chkstop_in 6 chkstop_in 6 8 tms tdo tdi tck tms tdo tdi tck 9 1 3 4 trst 7 16 2 10 12 (if any) cop header 14 4 key notes: 1. qack is an output and is not required at the cop header for emulation. 2. run/stop normally on pin 5 of the cop header is not implemented on the mpc8241. connect pin 5 of the cop header to ov dd with a 1- k pull-up resistor. 3. ckstp_out normally on pin 15 of the cop header is not implemented on the mpc8241. connect pin 15 of the cop header to ov dd with a 10-k pull-up resistor. 4. pin 14 is not physically present on the cop header. qack 1 ov dd ov dd 10 k ov dd trst 7 10 k ov dd 10 k 10 k 5. sreset functions as output sdma12 in extended rom mode. 6. chkstop_in functions as output sdma14 in extended rom mode. mpc8241 3 13 9 5 1 6 10 2 15 11 7 16 12 8 4 key no pin cop connector physical pin out 1 7. the cop port and target board should be able to independently assert hreset and trst to . the processor to fully control the processor as shown. 8. if the jtag interface is implemented, connect hreset from the target source to trst from the cop header through an and gate to trst of the part. if the jtag interface is not implemented, connect hreset from the target source to trst of the part through a 0- isolation resistor. 0 8
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 47 system design information 7.7 thermal management this section provides thermal manage ment information for the plastic ball grid array (pbga) package for air-cooled applications. depending on the application environment a nd the operating frequency, a heat sink may be required to maintain junction temperature within specifications. proper thermal control design primarily depends on the system-level design: heat sink, airflow, and thermal interface material. to reduce the die-junction temperature, heat sinks can be attached to the package by several methods: adhesive, spring clip to holes in the printed-circuit board or package, or mounting clip and screw assembly (see figure 28 ). figure 28. package exploded cross-sectional view with several heat sink options figure 29 depicts the die junction-to-ambient th ermal resistance for four typical cases: ? a heat sink is not attached to the pbga package and a high board-level thermal loading from adjacent components exists (label used?1s). ? a heat sink is not attached to the pbga package and a low board-level thermal loading from adjacent components exists (label used?2s2p). ? a large heat sink (cross cut extrusion, 38 38 16.5 mm) is attached to the pbga package and a high board-level thermal loading from adjacent components exists (label used?1s/sink). ? a large heat sink (cross cut extrusion, 38 38 16.5 mm) is attached to the pbga package and a low board-level thermal loading from adjacent components exists (label used?2s2p/sink). adhesive or thermal interface heat sink pbga package heat sink clip printed-circuit board option material die wire
mpc8241 integrated processor hardware specifications, rev. 10 48 freescale semiconductor system design information figure 29. die junction-to-ambient resistance the board designer can choose among several types of heat sinks to place on the mpc8241. several commercially available heat sinks for the mpc8241 are provided by the following vendors: aavid thermalloy 603-224-9988 80 commercial st. concord, nh 03301 internet: www.aavidthermalloy.com alpha novatech 408-749-7601 473 sapena ct. #15 santa clara, ca 95054 internet: www.alphanovatech.com international electronic research corporation (ierc) 818-842-7277 413 north moss st. burbank, ca 91502 internet: www.ctscorp.com tyco electronics 800-522-6752 chip coolers? p.o. box 3668 harrisburg, pa 17105-3668 internet: www.chipcoolers.com wakefield engineering 603-635-5102 33 bridge st. pelham, nh 03076 internet: www.wakefield.com selection of an appropriate heat sink depends on th ermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and co st. other heat sinks offered by aavid thermalloy, alpha novatech, ierc, chip coolers, and wakefield engineering offer different heat sink-to-ambient thermal resistances, and may or may not need airflow. 0.0 10.0 20.0 30.0 40.0 50.0 00.5 11.5 22.5 airflow v elocity (m/s) die junction-to-ambient thermal resistance (c/w) 1s 2s2p 1s/sink 2s2p/sink die junction-to-ambient thermal resistance (c/w) airflow velocity (m/s)
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 49 system design information 7.7.1 internal package conduction resistance for the pbga, die-up, packaging technology, shown in figure 28 , the intrinsic conduction thermal resistance paths are as follows: ? the die junction-to-case thermal resistance ? the die junction-to-ball thermal resistance figure 30 depicts the primary heat transfer path for a pa ckage with an attached heat sink mounted to a printed-circuit board. figure 30. pbga package with heat sink mounted to a printed-circuit board for this die-up, wire-bond pbga package, heat gene rated on the active side of the chip is conducted mainly through the mold cap, the heat sink attach ma terial (or thermal interf ace material), and finally through the heat sink where forced-air convection removes it. 7.7.2 adhesives and thermal interface materials a thermal interface material should be used between the top of the mold cap and the bottom of the heat sink minimizes thermal contact resistance. for applications that attach the heat sink by a spring clip mechanism, figure 31 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, a nd a joint with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. thermal grease significantly reduces the interface thermal resistance. that is, the bare joint offers a thermal resistance approximately seven times greater than the thermal grease joint. a spring clip attaches heat sinks to holes in the printed-circuit board (see figure 28 ). therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. the selection of any thermal interface material depends on fact ors such as thermal performance requirements, manufacturability, service temperature, dielectric properties, and cost. external resistance external resistance internal resistance radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package (note the internal versus external package resistance)
mpc8241 integrated processor hardware specifications, rev. 10 50 freescale semiconductor system design information figure 31. thermal performance of select thermal interface material the board designer can choose among several types of th ermal interface. heat sink adhesive materials are selected on the basis of high conductivity and ade quate mechanical strength to meet equipment shock/vibration requirements. severa l commercially-available thermal interfaces and adhesive materials are provided by the following vendors: the bergquist company 800-347-4572 18930 west 78 th st. chanhassen, mn 55317 internet: www.bergquistcompany.com chomerics, inc. 781-935-4850 77 dragon ct. woburn, ma 01888-4014 internet: www.chomerics.com dow-corning corporation 800-248-2481 dow-corning electronic materials 2200 w. salzburg rd. midland, mi 48686-0997 internet: www.dow.com 0 0.5 1 1.5 2 0 1020304050607080 silicone sheet (0.006 in.) bare joint floroether oil sheet (0.007 in.) graphite/oil sheet (0.005 in.) synthetic grease contact pressure (psi) specific thermal resistance (k-in. 2 /w)
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 51 system design information shin-etsu microsi, inc. 888-642-7674 10028 s. 51st st. phoenix, az 85044 internet: www.microsi.com thermagon inc. 888-246-9050 4707 detroit ave. cleveland, oh 44102 internet: www.thermagon.com 7.7.3 heat sink usage an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + (r ja p d ) where: t a = ambient temperature for the package ( c) r ja = junction-to-ambient thermal resistance ( c/w) p d = power dissipation in the package (w) the junction-to-ambient thermal resistance is an i ndustry-standard value that provides a quick and easy estimation of thermal performance. unfortunately, two values are in common usage: the value determined on a single-layer board and the value obtained on a board with two planes. for packages such as the pbga, these values can be different by a factor of two. wh ich value is closer to the application depends on the power dissipated by other components on the board . the value obtained on a single-layer board is appropriate for the tightly packed printed-circuit board. the value obtained on the board with the internal planes is usually appropriate if the board has low pow er dissipation and the components are well separated. when a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: r ja = r jc + r ca where: r ja = junction-to-ambient thermal resistance ( c/w) r jc = junction-to-case thermal resistance ( c/w) r ca = case-to-ambient thermal resistance ( c/w) r jc is device-related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r ca . for instance, the user can change the size of the heat sink, the airflow around the device, the interface materi al, the mounting arrangement on the printed-circuit board, or the thermal dissipation on the pr inted-circuit board surrounding the device. to determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter ( jt ) measures the temperature at the top center of the package case using the following equation: t j = t t + ( jt p d )
mpc8241 integrated processor hardware specifications, rev. 10 52 freescale semiconductor ordering information where: t t = thermocouple temperature atop the package ( c) jt = thermal characterization parameter ( c/w) p d = power dissipation in package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the packag e. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. when a heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearance minimizes the change in thermal performance that is caused by removing part of the th ermal interface to the heat sink. considering the experimental difficulties with this technique, many engineers measure th e heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. from this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. in many cases, it is appropriate to simulate the sy stem environment using a computational fluid dynamics thermal simulation tool. in such a tool, the simplest thermal model of a package that has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. the junction-to-case covers the situation where a heat sink is used or a substantial amount of heat is dissipated from the top of the package. the junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed-circuit board. 7.8 references semiconductor equipment and materials international 805 east middlefield rd. mountain view, ca 94043 (415) 964-5111 mil-spec and eia/jesd (jedec) specifications are available from global engineering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org. 8 ordering information ordering information for the parts that this document fully covers is provided in section 8.1, ?part numbers fully addressed by this document.? section 8.2, ?part numbers not fully addressed by this document,? lists the part numbers which do not fully conf orm to the specifications of this document. these special part numbers require an additional document called a hardware specifications addendum.
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 53 ordering information 8.1 part numbers fully addressed by this document table 19 provides the freescale part numbering nomenclatur e for the mpc8241. note that the individual part numbers correspond to a maximum processor core frequency. for available fr equencies, contact your local freescale sales office. in addition to the processor frequency, the part numbering scheme also includes an application modifier that may specify sp ecial application conditions. each part number also contains a revision code that refers to the die mask revision number. read the revision id register at address offset 0x08 to determine the revision level. 8.2 part numbers not fully addressed by this document parts with application modifiers or revision levels not fully addressed in this specification document are described in separate hardware specifications a ddendums that supplement and supersede this document (see table 20 ). table 19. part numbering nomenclature mpc nnnn l xx nnn x product code part identifier process descriptor package 1 processor frequency 2 (mhz) revision level mpc 8241 l = standard spec. 0 to 105 c zq = thick substrate and thick mold cap pbga (two layers) 166, 200 1.8 v 100 mv d:1.4 = rev. id:0x14 zq = thick substrate and thick mold cap pbga (four layers, thermally enhanced) 266 1.8 v 100 mv vr = lead-free version of package 166, 200, 266 1.8 v 100 mv notes: 1. see section 5, ?package description,? for more information on available package types. 2. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specification support all core frequencies. additionally, parts addressed by hardware specifications addendums may support other maximum core frequencies. table 20. part numbers addressed by mpc8241txxpns series (document no. MPC8241ECso1ad)) mpc nnnn t xx nnn x product code part identifier process descriptor package 1 processor frequency 2 (mhz) revision level processor version register value
mpc8241 integrated processor hardware specifications, rev. 10 54 freescale semiconductor document revision history 8.3 part marking parts are marked as the example shown in figure 32 . figure 32. part marking for mpc8241 device 9 document revision history table 21 provides a revision history for this hardware specification. mpc 8241 t = extended temperature spec. ?40 to 105 c zq = thick substrate and thick mold cap pbga (two layers) 166, 200 @ 1.8 v 100mv d:1.4 = rev. id:0x14 0x80811014 notes: 1. see section 5, ?package description,? for more information on available package types. 2. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specification support all core frequencies. additionally, parts addressed by hardware specifications addendums may support other maximum core frequencies. table 21. revision history table revision date substantive change(s) 10 02/2009 in ta b l e 1 6 , ?mpc8241 pinout listing,? added footnote 10 to pmaa[2]. in ta b l e 1 6 , ?mpc8241 pinout listing,? removed footnote 12 for second listing of rcs3 /trig_out . 9 09/2007 completely replaced section 4.6 with compliant i 2 c specifications as with other related integrated processor devices. section 7.6, ?jtag configuration signals ? reworded paragraph beginning ?the arrangement shown in figure 27 .. .? table 20. part numbers addressed by mpc8241txxpns series (document no. MPC8241ECso1ad)) mpc nnnn t xx nnn x notes : atwlyyww is traceability code. mpc8241lxxnnnx mmmmm atwlyyww ccccc mmmmm is the 5-digit mask number. ccccc is the country code.
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 55 document revision history 8 12/19/2005 document?imported new template and made minor editoral corrections. section 4.3.1?before figure 7, added paragraph for using dll mode that provides lowest locked tap point read in 0xe3. section 4.3.2?after figure 12, added a sentence to introduce figure 13. section 4.3.3?after table 11, added a sentence to introduce figure 14. section 4.3.4?after table 13, added to the sentence to introduce figures 16 thru 19. section 4.3.6?after table 16, added a sentence to introduce figures 22 thru 25. section 5.3?updated the driver and i/o assignment information for the multiplexed pci clock and duart signals. added note for hrst_cpu and hrst_ctrl, which had been mentioned only in figure 2. section 9.2?updated the part ordering specifications for the extended temperature parts. also updated section 9.2 to reflect what we offer for new orders. updated figure 34 to match with current part marking format. section 8.3?added new section for part marking information. 7 05/11/2004 section 4.1.4 ?table 4: changed the default for drive strength of drv_std_mem. section 4.3.1 ?table 8: changed the wording for item 15 description. section 4.3.4 ?table 10: changed t os range and wording in note 7; figure 11: changed wording for sdram_sync_in description relative to t os . 6.1 ? section 4.3.1 ? table 9: corrected last row to state the correct description for the bit setting: max tap delay, dll extend. figure 8: corrected the label name for the dll graph to state ?dll locking range loop delay vs. frequency of operation for dll_extend=1 and normal tap delay? 6 ? section 4.1.2 ? figure 2: added note 6 and related label for latching of the pll_cfg signals. section 4.1.3 ? updated specifications for the input high and input low voltages of pci_sync_in. section 4.3.1 ? table 8: corrected typo for first number 1a to 1; updated characteristics for the dll lock range for the default and remaining three dll locking modes; reworded note description for note 6. replaced contents of table 9 with bit descriptions for the four dll locking modes. in figures 7 through 10, updated the dll locking mode graphs. section 4.3.2 ? table 10: changed the name of references for timing parameters from sdram_sync_in to sys_logic_clk to be consistent with figure 11. followed the same change for note 2. section 4.3.3? table 11: changed the name of references for timing parameters from sdram_sync_in to sys_logic_clk to be consistent with figure 11. followed the same change for note 2. section 5.3 ? table 17: removed extra listing of drdy in test/configuration signal list and updated relevant notes for signal in memory interface signal listing. updated note #20. added note 24 for the signals of the uart interface. section 7.6 ? added relevant notes to this section and updated figure 29. 5 ? section 5.1? updated package information to include all package offerings. section 5.2 ? included package case outline for zp (rev. b) packaging parts. section 9 ? updated part markings for the offerings of the mpc8241. all sections ? nontechnical reformatting table 21. revision history table (continued) revision date substantive change(s)
mpc8241 integrated processor hardware specifications, rev. 10 56 freescale semiconductor document revision history 4 ? section 1.4.1.2?table 2: changed note 1. figure 2: updated note 2 and removed ?voltage regulator delay? label since section 1.7.2 is being deleted this revision. also, updated table 5, note 1 to reflect deletion of section 1.7.2. section 1.4.1.3?table 3: updated the maximum input capacitance from 15 to 16 pf based on characterization data. section 1.4.3.1?updated pci_sync_in jitter specifications to 200 ps. section 1.4.3.3?table 11, item 12b: added the word ?address? to help clarify which signals the spec applies to. figure 15: edited timing for items 12a0 and 12a2 to correspond with table 11. section 1.5.2?changed some dimension values for the side view of package. section 1.5.3?updated notes for the qack /da0 signal because this signal has been found to have no internal pull resistor. section 1.6?updated note numbering list for table 19. removed mode 5 from pll tables since that mode is no longer supported. section 1.7.2 ?this section was removed as it was not necessary since the power information is covered in section 1.4.1.5. section 1.7.4?added the words ?the clamping voltage? to describe lv dd in the sixth paragraph. changed the qack /da0 signal from the list of signals having an internal pull-up resistor to the list of signals needing a weak pull-up resistor to ov dd . section 1.9.1?table 21: added processor version register value column. 3 ? section 1.4.1.2?changed recommended value in table 2 for i/o buffer supply to 3.3 0.3 v. changed wording referencing figure 4 to refer to the mpc8241. section 1.4.2?table 6: updated values for thermal characterization data as per the new packaging and 266-mhz part. added note 7 for the difference between the 166-/200-mhz and the 266-mhz packaging. section 1.4.3?corrected the voltage listing for the 266-mhz part to 1.8 0.1 v in table 7. section 1.5?changed package parameters and illustration based on new packaging. section 1.6?table 18: modified pll configuration for 166- and 200-mhz parts for mode 7 to specify that this mode is not available for rev. d of the part. added sentence to note 1 referencing update for mode 7. table 19: made several range updates for various modes to accommodate vco limits. added mode 7 and 1e updates for rev. d. updated vco limits listed in notes 4, 6, and 7. 2 ? section 1.4.1.2?updated note 1 to include 266-mhz part. added a line to cautions 2 and 3 in the notes section of table 2. added figures 4 and 5 to show the overshoot and undershoot requirements for the pci interface. section 1.4.1.3?table 3: updated minimum value for input high voltage, and maximum value for capacitance. section 1.4.3.2?appended figures 9 and 10. section 1.4.3.4?added a column to table 13 to include 133-mhz memory bus speed for 266-mhz part. section 1.5.2?changed figure 24 to accommodate new package offerings. section 1.6?added table 19 for pll of the 266-mhz part. section 1.7.7?corrected note numbering in cop connector diagram. section 1.9.1?updated package description in part marking nomenclature. table 21. revision history table (continued) revision date substantive change(s)
mpc8241 integrated processor hardware specifications, rev. 10 freescale semiconductor 57 document revision history 1 ? updated document template. section 1.4.1.5?updated driver type names in table 4 so that they are consistent with the driver types referred to in the mpc8245 integrated processor reference manual . added notes 5 and 6 to table 4. section 1.4.3.1?added reference to an2164 in note 7. labeled n value in figures 5 through 8. section 1.4.3.2?updated figure 9 to show t os . table 9?changed default for 0x77 bits 5:4 to 0b10. section 1.4.3.3?added item 12e to table 10 for sdram_sync_in to output valid timing. updated figure 13 to state gv dd _ov dd instead of ov dd . section 1.5.3?updated driver type names to match those used in table 4. updated notes for the following signals: drdy , sdram_clk[0:3], miv , rtc, tdo, and da[11]. section 1.6?updated pll table and notes. removed old section 1.7.2 on voltage sequencing requirements. added cautions regarding voltage sequencing to the end of table 2 in section 1.4.1.2. section 1.7.3?changed sentence recommendation regarding decoupling capacitors. section 1.7.5?added reference to an2164. section 1.7.6?added sentence regarding the pll_cfg signals. removed old section 1.7.8 since the mpc8241 cannot be used as a drop in replacement for the mpc8240 because of pin compatibility issues. section 1.7.8?updated trst information in this section and figure 26. section 1.7.9?updated list for heat sink and thermal interface vendors. section 1.9?changed format of ordering information section. added tables to reflect part number specifications also available. added sections 1.9.2 and 1.9.3. 0.3 ? corrected solder ball information in section 1.5.1 to 62 sn/36 pb/2 ag. section 1.4.3.1?corrected dll_extend labeling in figures 5 through 8. removed note for pin trig_out/rcs3 in table 16, as well as from the list of pins needing to be pulled up to iv dd in section 1.7.6. corrected order information labeling in section 1.9 to mpc8241xzpxxxx. also corrected label description of zu = pbga to zp = pbga. 0.2 ? table 16?corrected pin number for pll_cfg0/da10 to n3. the pin was already correctly listed for da10/pll_cfg0. updated note 1 to reflect pin assignments for the mpc8241. updated footnotes throughout document. section 1.4.3.3?updated note 4 to correct bit values of pci_hold_del in pmcr2. section 1.6?updated notes in table 17. included memory vco minimum and maximum numbers. section 1.7.8?updated description of bits pci_hold_del in pmcr2. section 1.7.10.3?replaced thermal characterization parameter (yjt) with correct thermal characterization parameter ( jt ). changed symbol to jt . 0.1 ? updated features list in section 1.2. corrected pin assignments in table 16 for da[15] and dqm[3] signals. added vendor (cool innovations, inc.) to list of heat sink vendors. 0 ? initial release. table 21. revision history table (continued) revision date substantive change(s)
document number: MPC8241EC rev. 10 02/2009 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com freescale and the freescale logo are trademarks or registered trademarks of freescale semiconductor, inc. in the u.s. and other countries. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ieee 1149.1 is a registered trademark of the institute of electrical and electronics engineers, inc. (ieee). this product is not endorsed or approved by the ieee. ? freescale semiconductor, inc., 2009. all rights reserved.

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